String Matching on Multicontext FPGA using Dynamic Partial Reconfiguration

If logic be optimized for each problem instance, FPGAs do better than ASICs. CAD tools to generate problem instance dependent logic and time required configuring the FPGAs. In this paper, a novel approach for mapping and reconfiguration proposed that uses dynamic partial reconfiguration of FPGAs to do speed-up over existing approaches. Main idea is to design and map problem instance dependent logic on FPGA that maps problem instance dependent logic on other contexts of the same FPGA. As a result, CAD tools needed to use just once for each problem and not once for every problem instance as is usually done. To prove this approach, a detailed implementation of snort rule set based IDS using Boyer-Moore (BM) string matching algorithm presented. It implemented to get correct estimates of performance on FPGA device. Speedups in mapping time of approx. 10 over CAD tools and dynamic reconfiguration time 0.016 ms for 8 patterns obtained. Significant speedups obtained in overall mapping time as well including a speed up ranging from 3 to 16 times over a software implementation of snort rule set based IDS using BM algorithm running on a Pentium @ 2.8GHz workstation. Keywords— partial reconfiguration, context switching, Dynamic reconfiguration, Field programmable gate arrays